Array substrate, manufacturing method thereof, flexible display panel and display device

ABSTRACT

The present disclosure provides an array substrate, a manufacturing method thereof, a flexible display panel and a display device, for achieving frame-free full-screen flexible display product. The array substrate provided in the present disclosure comprises a flexible base substrate, a thin film transistor on a first surface of the flexible base substrate, and a wiring terminal for transmitting a signal to an electrode of the thin film transistor on a second surface of the flexible base substrate opposite to the first surface, wherein the electrode of the thin film transistor is electrically connected to the wiring terminal through a via hole penetrating the flexible base substrate.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Chinese Patent ApplicationNo. 201710433423.6, filed on Jun. 9, 2017, the entirety of which isincorporated herein by reference.

BACKGROUND

The present disclosure relates to the technical field of displays, andparticularly to an array substrate, a manufacturing method thereof, aflexible display panel, and a display device.

The field of display technology is developing rapidly. With thecontinuous increase in demand for various display products such asnotebooks, smartphones, televisions, tablet computers, smart watches,fitness wristbands and the like, more novel display products will emergein future.

At present, most flexible display panels have frames, and wiringterminals (for example, for binding PAD) are usually disposed on theouter periphery of the display area of the flexible display panel.Frame-free full-screen display products allow better viewing experiencesof users, and are likely to drive new consumer markets. On this basis,there exists an urgent technical need to achieve a frame-freefull-screen flexible display product.

SUMMARY

Embodiments of the present disclosure provide an array substrate, amanufacturing method thereof, a flexible display panel and a displaydevice, for achieving a frame-free full-screen flexible display product.

Embodiments of the present disclosure provide an array substratecomprising: a flexible base substrate, a thin film transistor on a firstsurface of the flexible base substrate, and a wiring terminal fortransmitting a signal to an electrode of the thin film transistor, on asecond surface of the flexible base substrate opposite to the firstsurface, wherein the electrode of the thin film transistor iselectrically connected to the wiring terminal through a via holepenetrating the flexible base substrate.

In an embodiment, the array substrate further comprises a signal wire onthe first surface or the second surface of the flexible base substrate;wherein the wiring terminal is connected to the electrode of the thinfilm transistor through the signal wire.

In an embodiment, the signal wire comprises a plurality of gateelectrode signal wires and a plurality of data signal wires insulatedfrom each other.

In an embodiment, the signal wire is disposed on the first surface ofthe flexible base substrate, a plurality of wiring terminals areprovided, and a first insulating layer is disposed between the gateelectrode signal wires and the flexible base substrate, wherein eachgate electrode signal wire is connected to each wiring terminal in oneto one correspondence through a via hole penetrating the firstinsulating layer and the flexible base substrate.

In an embodiment, a second insulating layer is disposed between the datasignal wires and the flexible base substrate, and each data signal wireis connected to each wiring terminal in one to one correspondencethrough a via hole penetrating the second insulating layer and theflexible base substrate.

In an embodiment, the gate electrode signal wires are disposed in thesame layer as that of a gate electrode, and the data signal wires aredisposed in the same layer as that of source/drain electrodes.

In an embodiment, the gate electrode is positioned between thesource/drain electrodes and the flexible base substrate, and an activelayer is disposed between the gate electrode and the flexible basesubstrate; the first insulating layer comprises: a buffer layer betweenthe active layer and the flexible base substrate, and a gate insulatinglayer between the gate electrode and the active layer, and the secondinsulating layer comprises: the buffer layer, the gate insulating layer,and an interlayer dielectric layer between the source/drain electrodesand the gate electrode.

In an embodiment, the gate electrode is positioned between thesource/drain electrodes and the flexible base substrate, and an activelayer is disposed between the gate electrode and the source/drainelectrodes; the first insulating layer comprises a buffer layer betweenthe gate electrode and the flexible base substrate, and the secondinsulating layer comprises the buffer layer, and a gate insulating layerbetween the gate electrode and the active layer.

In an embodiment, the source/drain electrodes are positioned between thegate electrode and the flexible base substrate, and an active layer isdisposed between the source/drain electrodes and the flexible basesubstrate; the second insulating layer comprises a buffer layer betweenthe active layer and the flexible base substrate, and the firstinsulating layer comprises the buffer layer, and a gate insulating layerbetween the gate electrode and the source/drain electrodes.

Embodiments of the present disclosure further provide a flexible displaypanel comprising: the array substrate provided in any embodiment of thepresent disclosure, and a flexible circuit board or integrated circuiton the second surface of the flexible base substrate; wherein theflexible circuit board or integrated circuit is electrically connectedto an electrode of the thin film transistor through the wiring terminal.

Embodiments of the present disclosure further provide a display devicecomprising the flexible display panel provided in any embodiment of thepresent disclosure.

Embodiments of the present disclosure further provide a manufacturingmethod of an array substrate, comprising: forming a wiring terminal fortransmitting a signal to an electrode of a thin film transistor, on arigid substrate; forming a flexible base substrate on the rigidsubstrate with the wiring terminal formed thereon; and forming a thinfilm transistor on the flexible base substrate, wherein an electrode ofthe thin film transistor is electrically connected to the wiringterminal through a via hole penetrating the flexible base substrate.

In an embodiment, after forming the wiring terminal and before formingthe flexible base substrate, the method further comprises forming asignal wire on the rigid substrate with the wiring terminal formedthereon; or after forming the flexible base substrate, the methodfurther comprises forming a signal wire on the flexible base substrate,wherein the wiring terminal is to be connected to an electrode of thethin film transistor through the signal wire.

In an embodiment, the signal wire comprises a plurality of gateelectrode signal wires and a plurality of data signal wires insulatedfrom each other; a plurality of wiring terminals are provided; andforming the plurality of gate electrode signal wires on the flexiblebase substrate comprises: forming a first insulating layer on theflexible base substrate; forming a via hole at a position on the firstinsulating layer and the flexible base substrate corresponding to eachof the wiring terminals to be connected to the gate electrode signalwires; and forming a plurality of gate electrode signal wires on thefirst insulating layer with the via hole formed thereon, wherein eachgate electrode signal wire is connected to each wiring terminal in oneto one correspondence through a via hole penetrating the firstinsulating layer and the flexible base substrate.

In an embodiment, forming a plurality of data signal wires on theflexible base substrate comprises: forming a second insulating layer onthe flexible base substrate; forming a via hole at a position on thesecond insulating layer and the flexible base substrate corresponding toeach of the wiring terminals to be connected to the data signal wires;and forming a plurality of data signal wires on the second insulatinglayer with the via hole formed thereon, wherein each data signal wire isconnected to each wiring terminal in one to one correspondence through avia hole penetrating the second insulating layer and the flexible basesubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural schematic diagram of an array substrate providedin an embodiment of the present disclosure.

FIG. 2 is a structural schematic diagram of another array substrateprovided in an embodiment of the present disclosure.

FIG. 3 is a structural schematic diagram of yet another array substrateprovided in an embodiment of the present disclosure.

FIG. 4 is a schematic flow chart of a manufacturing method of an arraysubstrate provided in an embodiment of the present disclosure.

FIG. 5(a) to FIG. 5(h) are schematic flow charts of a manufacturingprocess of an array substrate provided in an embodiment of the presentdisclosure.

FIG. 6 is a structural schematic diagram of a flexible display panelprovided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide an array substrate, amanufacturing method thereof, a flexible display panel, and a displaydevice for achieving a frame-free full-screen flexible display product.

The technical solutions in embodiments of the present disclosure will bedescribed in detail below in combination with the drawings of theembodiments of the present disclosure. The embodiments described indetail herein constitute only a part of, not all of the embodimentscontemplated in view of the present disclosure. All of other embodimentsobtained by those skilled in the art based on the embodiments of thepresent disclosure, without inventive efforts, fall within theprotection scope of the present invention.

It should be noted that that the drawings are not necessarily to scale.For example, the thickness and shape of each layer in the drawings ofthe present disclosure does not indicate a real proportion, and is onlyintended to schematically illustrate the present disclosure.

Referring to FIG. 1, an embodiment of the present disclosure provides anarray substrate comprising: a flexible base substrate 11, a thin filmtransistor 15 (as indicated by the dashed box in FIG. 1) and a signalwire 12 disposed on a first surface of the flexible base substrate 11,and a wiring terminal 13 for transmitting a signal to an electrode ofthe thin film transistor 15 disposed on a second surface of the flexiblebase substrate 11 opposite to the first surface, wherein one end of thesignal wire 12 is connected to the electrode of the thin film transistor15, and the other end is connected to the wiring terminal 13 through avia hole 14 penetrating the flexible base substrate 11.

Here, the signal wire 12 may comprise a plurality of gate electrodesignal wires 121 and a plurality of data signal wires 122 insulated fromeach other.

The signal wire 12, for example, may also comprise a clock signal wire,and this is not limited in the embodiments of the present disclosure.

If an insulating layer is further disposed between the signal wire 12and the flexible base substrate 11, the signal wire 12 is connected tothe wiring terminal 13 through a via hole penetrating the insulatinglayer and the flexible base substrate 11.

As shown in FIG. 1, the thin film transistor 15 comprises an activelayer 151, a gate insulating layer (GI) 152, a gate electrode 153, aninterlayer dielectric layer (ILD) 154 and source/drain electrodes 155sequentially stacked on the flexible base substrate 11.

As shown in FIG. 1, a plurality of wiring terminals 13 are provided, anda first insulating layer is disposed between the gate electrode signalwire 121 and the flexible base substrate 11, and each gate electrodesignal wire 121 is connected to one wiring terminal 13 through a viahole 141 penetrating the first insulating layer and the flexible basesubstrate 11.

As shown in FIG. 1, a second insulating layer is disposed between thedata signal wire 122 and the flexible base substrate 11, and each datasignal wire 122 is connected to one wiring terminal 13 through a viahole 142 penetrating the second insulating layer and the flexible basesubstrate 11.

In a particular embodiment, as shown in FIG. 1, the gate electrodesignal wire 121 is disposed in the same layer as that of the gateelectrode 153, and the data signal wire 122 is disposed in the samelayer as that of the source/drain electrodes 155.

In a particular embodiment, as shown in FIG. 1, a buffer layer (Buffer)16 is disposed between the active layer 151 and the flexible basesubstrate 11; the first insulating layer comprises the buffer layer 16and the gate insulating layer 152; and the second insulating layercomprises the buffer layer 16, the gate insulating layer 152 and theinterlayer dielectric layer 154.

Further, the signal wire 12 may also be disposed on the second surfaceof the flexible base substrate 11. In this case, one end of the signalwire 12 is connected to the wiring terminal 13, and the other end isconnected to an electrode of the thin film transistor 15 through the viahole 14 disposed in the flexible base substrate 11.

Referring to FIG. 2, an embodiment of the present disclosure furtherprovides an array substrate, which is similar to the array substrate asshown in FIG. 1. The same portions are not reiterated here, and onlydifferent portions are described below.

In the array substrate as shown in FIG. 2, the thin film transistor 15(as indicated by the dashed box in FIG. 2) comprises a gate electrode153, a gate insulating layer 152, an active layer 151 and source/drainelectrodes 155 sequentially stacked on the flexible base substrate 11.

In a particular embodiment, as shown in FIG. 2, a buffer layer 16 isdisposed between the gate electrode 153 and the flexible base substrate11; the first insulating layer comprises the buffer layer 16; and thesecond insulating layer comprises the buffer layer 16 and the gateinsulating layer 152.

Of course, it is possible that no buffer layer 16 is disposed betweenthe gate electrode 153 and the flexible base substrate 11. In this case,there is no first insulating layer between the gate electrode signalwire 121 and the flexible base substrate 11, that is, the gate electrodesignal wire 121 is connected to the wiring terminal 13 only through avia hole disposed in the flexible base substrate 11, and this is notlimited in the embodiments of the present disclosure.

Referring to FIG. 3, an embodiment of the present disclosure furtherprovides an array substrate, which is similar to the array substrate asshown in FIG. 1. The same portions are not reiterated here, and onlydifferent portions are described below.

In the array substrate as shown in FIG. 3, the thin film transistor 15(as indicated by the dashed box in FIG. 3) comprises an active layer151, source/drain electrodes 155, a gate insulating layer 152 and a gateelectrode 153 sequentially stacked on the flexible base substrate 11.

In a particular embodiment, as shown in FIG. 3, a buffer layer 16 isdisposed between the active layer 151 and the flexible base substrate11; the second insulating layer comprises the buffer layer 16; and thefirst insulating layer comprises the buffer layer 16 and the gateinsulating layer 152.

Base on the same concept, as shown in FIG. 4, an embodiment of thepresent disclosure further provides a manufacturing method of an arraysubstrate, comprising the following steps:

S101: Forming a wiring terminal for transmitting a signal to anelectrode of a thin film transistor on a rigid substrate; wherein therigid substrate may be a glass substrate, a quartz substrate, a rockcrystal substrate, or the like.

The material of the wiring terminal may be, for example, a metalmaterial such as molybdenum (Mo), aluminum (Al), copper (Cu) and thelike.

Forming the wiring terminal on the rigid substrate may comprise: forminga metal layer on the rigid substrate by sputtering; and patterning themetal layer to form the wiring terminal.

S102: Forming a flexible base substrate on the rigid substrate with thewiring terminal formed thereon; wherein, the flexible base substrate maybe a transparent organic insulating substrate composed of one selectedfrom the group consisting of polyethersulfone (PES), polyacrylate (PAR),polyetherimide (PEI), polyethelyene naphthalate (PEN), polyethyleneterephthalate (PET), polyphenylene sulfide (PPS), polyallylate,polyimide resin (PI), polycarbonate (PC), cellulose triacetate (TAC),cellulose acetate propionate (CAP), acrylate and a combination thereof.

S103: Forming a thin film transistor on the flexible base substrate,wherein an electrode of the thin film transistor is electricallyconnected to the wiring terminal through a via hole penetrating theflexible base substrate.

In a particular embodiment, after forming the wiring terminal and beforeforming the flexible base substrate, the method may further comprise:forming a signal wire on the rigid substrate with the wiring terminalformed thereon; wherein the wiring terminal is to be connected to anelectrode of the thin film transistor through the signal wire.

In another particular embodiment, after forming the flexible basesubstrate, the method may further comprise: forming a signal wire on theflexible base substrate; wherein the wiring terminal is to be connectedto an electrode of the thin film transistor through the signal wire.

Here, the signal wire may comprise a plurality of gate electrode signalwires and a plurality of data signal wires insulated from each other,and a plurality of wiring terminals may be provided.

In a particular embodiment, forming a plurality of gate electrode signalwires on the flexible base substrate may particularly comprise: forminga first insulating layer on the flexible base substrate; forming a viahole at a position on the first insulating layer and the flexible basesubstrate corresponding to each of the wiring terminals to be connectedto the gate electrode signal wires; and forming a plurality of gateelectrode signal wires on the first insulating layer with the via holeformed thereon, wherein each gate electrode signal wire is connected toeach wiring terminal in one to one correspondence through a via holepenetrating the first insulating layer and the flexible base substrate.

In a particular embodiment, forming a plurality of data signal wires onthe flexible base substrate may particularly comprise: forming a secondinsulating layer on the flexible base substrate; forming a via hole at aposition on the second insulating layer and the flexible base substratecorresponding to each of the wiring terminals to be connected to thedata signal wires; and forming a plurality of data signal wires on thesecond insulating layer with the via hole formed thereon, wherein eachdata signal wire is connected to each wiring terminal in one to onecorrespondence through a via hole penetrating the second insulatinglayer and the flexible base substrate.

It should be noted that if the data signal wire is above the gateelectrode signal wire, then the second insulating layer=the firstinsulating layer+a third insulating layer between the gate electrodesignal wire and the data signal wire. In the process of manufacturingthe array substrate, forming the plurality of gate electrode signalwires and the plurality of data signal wires insulated from each otheron the flexible base substrate may particularly comprise: forming afirst insulating layer on the flexible base substrate; on the firstinsulating layer and the flexible base substrate, forming a via hole ata position corresponding to each of the wiring terminals to be connectedto the gate electrode signal wires, and forming a via hole at a positioncorresponding to each of the wiring terminals to be connected to thedata signal wires; forming a plurality of gate electrode signal wires onthe first insulating layer with the via hole formed thereon; forming athird insulating layer on the flexible base substrate with the pluralityof gate electrode signal wires formed thereon; forming a via hole at aposition on the third insulating layer corresponding to each of thewiring terminals to be connected to the data signal wires; and forming aplurality of data signal wires on the third insulating layer with thevia hole formed thereon.

Here, the third insulating layer may be, for example, a gate insulatinglayer, an interlayer dielectric layer or the like.

In an embodiment, the area occupied by the via hole pattern of the thirdinsulating layer is not less than the area occupied by the via holepattern of the first insulating layer.

Forming the plurality of gate electrode signal wires and the pluralityof data signal wires insulated from each other on the flexible basesubstrate may further comprise: forming a first insulating layer on theflexible base substrate; forming a via hole at a position on the firstinsulating layer and the flexible base substrate corresponding to eachof the wiring terminals to be connected to the gate electrode signalwires; and forming a plurality of gate electrode signal wires on thefirst insulating layer with the via hole formed thereon; forming a thirdinsulating layer on the flexible base substrate with the plurality ofgate electrode signal wires formed thereon; forming a via hole at aposition on the third insulating layer, the first insulating layer andthe flexible base substrate corresponding to each of the wiringterminals to be connected to the data signal wires; and forming aplurality of data signal wires on the third insulating layer with thevia hole formed thereon.

Similarly, if the gate electrode signal wire is above the data signalwire, then the first insulating layer=the second insulating layer+athird insulating layer between the gate electrode signal wire and thedata signal wire. In the process of manufacturing the array substrate,forming the plurality of gate electrode signal wires and the pluralityof data signal wires insulated from each other on the flexible basesubstrate may particularly comprise: forming a second insulating layeron the flexible base substrate; on the second insulating layer and theflexible base substrate, forming a via hole at a position correspondingto each of the wiring terminals to be connected to the gate electrodesignal wires, and forming a via hole at a position corresponding to eachof the wiring terminals to be connected to the data signal wires;forming a plurality of data signal wires on the second insulating layerwith the via hole formed thereon; forming a third insulating layer onthe flexible base substrate with the plurality of gate electrode signalwires formed thereon; forming a via hole at a position on the thirdinsulating layer corresponding to each of the wiring terminals to beconnected to the gate electrode signal wires; and forming a plurality ofgate electrode signal wires on the third insulating layer with the viahole formed thereon.

In an embodiment, the area occupied by the via hole pattern of the thirdinsulating layer is not less than the area occupied by the via holepattern of the second insulating layer.

Forming the plurality of gate electrode signal wires and the pluralityof data signal wires insulated from each other on the flexible basesubstrate may further comprise: forming a second insulating layer on theflexible base substrate; forming a via hole at a position on the secondinsulating layer and the flexible base substrate corresponding to eachof the wiring terminals to be connected to the data signal wires; andforming a plurality of data signal wires on the second insulating layerwith the via hole formed thereon; forming a third insulating layer onthe flexible base substrate with the plurality of gate electrode signalwires formed thereon; forming a via hole at a position on the thirdinsulating layer, the second insulating layer and the flexible basesubstrate corresponding to each of the wiring terminals to be connectedto the gate electrode signal wires; and forming a plurality of gateelectrode signal wires on the third insulating layer with the via holeformed thereon.

The manufacturing process of an array substrate provided in anembodiment of the present disclosure will be described in detail belowwith reference to FIG. 5(a)˜FIG. 5(g), by taking an array substrateshown in FIG. 1 as an example.

Step I: Referring to FIG. 5(a), forming a wiring terminal 502 fortransmitting a signal to an electrode of a thin film transistor on aglass substrate 501. For example, a metal film layer may be deposited onthe glass substrate 501 by using a magnetron sputtering process; thematerial of the metal film layer may be Mo, Al, Cu or the like; and themetal film layer is patterned with a wet etching method usingphotoresist to form the wiring terminal 502.

Step II: Referring to FIG. 5(b), forming a flexible base substrate 503on the glass substrate 501 with the wiring terminal 502 formed thereon;wherein, the material of the flexible base substrate 503 is PI. Forexample, the flexible base substrate 503 is formed by spin coating a PIfilm layer on the glass substrate 501 with the wiring terminal 502formed thereon.

Step III: Referring to FIG. 5(c), forming a buffer layer 504, an activelayer 505, and a gate insulating layer 506 sequentially on the flexiblebase substrate 503. For example, a silicon nitride (SiN_(x)) layer and asilicon oxide (SiO_(x)) layer are sequentially deposited as the bufferlayer 504 on the flexible base substrate 503 with a plasma enhancedchemical vapor deposition (PECVD) method; an amorphous silicon (A-Si)layer is formed on the SiO_(x) layer, and the amorphous silicon, afterbeing dehydrogenated by high temperature annealing, is subjected tocrystallization treatment with an excimer laser crystallization (ELA)method, and then a poly-silicon (P-Si) pattern, as the active layer 505,is formed with a dry etching process using photoresist; the poly-siliconactive layer 505 is subjected to a threshold voltage heavy doping (VthDoping) with an ion injection process; and a silicon nitride (SiN_(x))layer and a silicon oxide (SiO_(x)) layer are sequentially deposited asthe gate insulating layer 506 on the active layer 505 with a PECVDmethod.

Step IV: Referring to FIG. 5(d), forming a via hole at a position on thegate insulating layer 506, the buffer layer 504 and the flexible basesubstrate 503 corresponding to each of the wiring terminals 502. Forexample, the gate insulating layer 506, the buffer layer 504 and theflexible base substrate 503 are patterned with a dry etching methodusing photoresist, to form the via hole at a position corresponding toeach of the wiring terminals 502.

Step V: Referring to FIG. 5(e), forming a plurality of gate electrodesignal wires 507, a gate electrode 508 and an interlayer dielectriclayer 509 sequentially on the gate insulating layer 506 with the viahole formed thereon; wherein, each gate electrode signal wire 507 isconnected to one wiring terminal 502 through a via hole penetrating thegate insulating layer 506, the buffer layer 504 and the flexible basesubstrate 503. For example, a Mo metal layer may be deposited with amagnetron sputtering process on the gate insulating layer 506 with thevia hole formed thereon, and patterned with a wet etching method usingphotoresist to form the plurality of gate electrode signal wires 507 andthe gate electrode 508; the poly-silicon active layer 505 is subjectedto source/drain heavy doping (S/D Doping) with an ion injection process;and a silicon nitride (SiN_(x)) layer and a silicon oxide (SiO_(x))layer are sequentially deposited as the interlayer dielectric layer 509on the plurality of gate electrode signal wires 507 and the gateelectrode 508 with a PECVD method.

Step VI: Referring to FIG. 5(f), for the interlayer dielectric layer509, forming a via hole at a position corresponding to each of thewiring terminals 502 to be connected to the data signal wires; and forthe interlayer dielectric layer 509 and the gate insulating layer 506,forming a via hole for connecting the active layer 505 and thesource/drain electrodes. For example, the interlayer dielectric layer509 is patterned with exposing and dry etching methods, to form a viahole at a position corresponding to each of the wiring terminals 502 tobe connected to the data signal wires; and the interlayer dielectriclayer 509 and the gate insulating layer 506 are patterned with exposingand dry etching methods to form a via hole for connecting the activelayer 505 and the source/drain electrodes.

Step VII: Referring to FIG. 5(g), forming a plurality of data signalwires 510 and source/drain electrodes 511 on the interlayer dielectriclayer 509 with the via hole formed thereon; wherein, each data signalwire 510 is connected to one wiring terminal 502 through a via holepenetrating the interlayer dielectric layer 509, the gate insulatinglayer 506, the buffer layer 504 and the flexible base substrate 503. Thesource/drain electrodes 511 and the active layer 505 are connectedthrough the via hole therebetween. For example, a Ti metal layer, an Almetal layer, and a Ti metal layer may be sequentially deposited with amagnetron sputtering process on the interlayer dielectric layer 509 withthe via hole formed thereon, and patterned with a dry etching methodusing photoresist to form the plurality of data signal wires 510 and thesource/drain electrodes 511.

Step VIII: Peeling off the glass substrate 501, wherein the arraysubstrate after peeling is as shown in FIG. 5(h).

Based on the same concept, referring to FIG. 6, an embodiment of thepresent disclosure further provides a flexible display panel comprising:an array substrate 61 provided in any embodiment of the presentdisclosure, and a flexible circuit board 62 disposed on a second surfaceof a flexible base substrate 611 of the array substrate 61; wherein theflexible circuit board 62 is connected to a signal wire 613 of the arraysubstrate 61 through a wiring terminal 612 of the array substrate 61,and the signal wire 613 is connected to an electrode of a thin filmtransistor of the array substrate 61. Here, the flexible circuit board62 may be replaced with an integrated circuit.

In a particular embodiment, as shown in FIG. 6, the above flexibledisplay panel may further comprise: a planarization layer (PLN) 63disposed on a thin film transistor 614 of the array substrate 61 and anorganic light emitting diode 64. Here, the organic light emitting diode64 may be replaced with a quantum dot light emitting diode.

Based on the same concept, an embodiment of the present disclosurefurther provides a display device comprising the flexible display panelprovided in any embodiment of the present disclosure. The display devicemay be any product or component having a displaying function such asmobile phone, tablet computer, television, display, notebook, digitalphoto frame, navigator and the like.

In summary, the embodiments of the present disclosure provide an arraysubstrate, a manufacturing method thereof, a flexible display panel anda display device. The array substrate comprises a flexible basesubstrate, a thin film transistor disposed on a first surface of theflexible base substrate, and a wiring terminal for transmitting a signalto an electrode of the thin film transistor disposed on a second surfaceof the flexible base substrate opposite to the first surface, whereinthe electrode of the thin film transistor is electrically connected tothe wiring terminal through a via hole penetrating the flexible basesubstrate. Since the wiring terminal is disposed on the back surface ofthe flexible base substrate, there is no need to reserve a space fordisposing the wiring terminal on the outer periphery of the display areaof the flexible display panel comprising the array substrate, saidwiring terminal being used to connect the flexible circuit board orintegrated circuit with the electrode of the thin film transistor. Thus,a frame-free full-screen flexible display product can be achieved.

Obviously, modifications and variations on the present disclosure can bemade by those skilled in the art without departing from the spirit andscope of the present invention. As such, if these modifications andvariations fall within the scopes of the claims of the presentapplication or equivalent technologies thereof, the present invention isintended to encompass these modifications and variations.

1. An array substrate comprising: a flexible base substrate; a thin filmtransistor on a first surface of the flexible base substrate; a wiringterminal for transmitting a signal to an electrode of the thin filmtransistor, on a second surface of the flexible base substrate oppositeto the first surface; and a signal wire on the first surface of theflexible base substrate, the signal wire comprising a plurality of gateelectrode signal wires and a plurality of data signal wires insulatedfrom each other, wherein the electrode of the thin film transistor iselectrically connected to the wiring terminal through the signal wireand a via hole penetrating the flexible base substrate.
 2. (canceled) 3.(canceled)
 4. The array substrate according to claim 1, wherein aplurality of wiring terminals are provided, and a first insulating layeris disposed between the gate electrode signal wires and the flexiblebase substrate, wherein each gate electrode signal wire is connected toeach wiring terminal in one to one correspondence through a via holepenetrating the first insulating layer and the flexible base substrate.5. The array substrate according to claim 4, wherein a second insulatinglayer is disposed between the data signal wires and the flexible basesubstrate, and each data signal wire is connected to each wiringterminal in one to one correspondence through a via hole penetrating thesecond insulating layer and the flexible base substrate.
 6. The arraysubstrate according to claim 5, wherein the gate electrode signal wiresare disposed in the same layer as that of a gate electrode, and the datasignal wires are disposed in the same layer as that of source/drainelectrodes.
 7. The array substrate according to claim 6, wherein thegate electrode is positioned between the source/drain electrodes and theflexible base substrate, and an active layer is disposed between thegate electrode and the flexible base substrate; the first insulatinglayer comprises a buffer layer between the active layer and the flexiblebase substrate and a gate insulating layer between the gate electrodeand the active layer, and the second insulating layer comprises thebuffer layer, the gate insulating layer, and an interlayer dielectriclayer between the source/drain electrodes and the gate electrode.
 8. Thearray substrate according to claim 6, wherein the gate electrode ispositioned between the source/drain electrodes and the flexible basesubstrate, and an active layer is disposed between the gate electrodeand the source/drain electrodes; the first insulating layer comprises abuffer layer between the gate electrode and the flexible base substrate,and the second insulating layer comprises the buffer layer, and a gateinsulating layer between the gate electrode and the active layer.
 9. Thearray substrate according to claim 5, wherein source/drain electrodesare positioned between a gate electrode and the flexible base substrate,and an active layer is disposed between the source/drain electrodes andthe flexible base substrate; the second insulating layer comprises abuffer layer between the active layer and the flexible base substrate,and the first insulating layer comprises the buffer layer, and a gateinsulating layer between the gate electrode and the source/drainelectrodes.
 10. The array substrate according to claim 1, wherein theflexible base substrate is a transparent organic insulating substrate.11. A flexible display panel comprising: the array substrate accordingto claim 1; and a flexible circuit board or integrated circuit on thesecond surface of the flexible base substrate, wherein the flexiblecircuit board or integrated circuit is electrically connected to anelectrode of the thin film transistor through the wiring terminal.
 12. Adisplay device comprising the flexible display panel according to claim11.
 13. A manufacturing method of the array substrate according to claim1, comprising: forming the wiring terminal on a rigid substrate; formingthe flexible base substrate on the rigid substrate with the wiringterminal formed thereon; and forming the thin film transistor and thesignal wire on the flexible base substrate.
 14. (canceled) 15.(canceled)
 16. (canceled)
 17. The manufacturing method according toclaim 13, wherein forming the gate electrode signal wires on theflexible base substrate comprises: forming a first insulating layer onthe flexible base substrate; forming a via hole at a position on thefirst insulating layer and the flexible base substrate corresponding toeach of the wiring terminals to be connected to the gate electrodesignal wires; and forming a plurality of gate electrode signal wires onthe first insulating layer with the via hole formed thereon, whereineach gate electrode signal wire is connected to each wiring terminal inone to one correspondence through a via hole penetrating the firstinsulating layer and the flexible base substrate.
 18. The manufacturingmethod according to claim 17, wherein forming the data signal wires onthe flexible base substrate comprises: forming a second insulating layeron the flexible base substrate; forming a via hole at a position on thesecond insulating layer and the flexible base substrate corresponding toeach of the wiring terminals to be connected to the data signal wires;and forming a plurality of data signal wires on the second insulatinglayer with the via hole formed thereon, wherein each data signal wire isconnected to each wiring terminal in one to one correspondence through avia hole penetrating the second insulating layer and the flexible basesubstrate.
 19. The manufacturing method according to claim 13, whereinafter forming the thin film transistor on the flexible base substrate,the method further comprises: peeling off the rigid substrate.
 20. Anarray substrate comprising: a flexible base substrate; a thin filmtransistor on a first surface of the flexible base substrate; a wiringterminal for transmitting a signal to an electrode of the thin filmtransistor, on a second surface of the flexible base substrate oppositeto the first surface; and a signal wire on the second surface of theflexible base substrate, said signal wire comprising a plurality of gateelectrode signal wires and a plurality of data signal wires insulatedfrom each other, wherein the electrode of the thin film transistor iselectrically connected to the wiring terminal through a via holepenetrating the flexible base substrate and the signal wire.
 21. Thearray substrate according to claim 20, wherein the flexible basesubstrate is a transparent organic insulating substrate.
 22. A flexibledisplay panel comprising: the array substrate according to claim 20; anda flexible circuit board or integrated circuit on the surface of theflexible base substrate, wherein the flexible circuit board orintegrated circuit is electrically connected to an electrode of the thinfilm transistor through the wiring terminal.
 23. A display devicecomprising the flexible display panel according to claim
 12. 24. Amanufacturing method of the array substrate according to claim 9,comprising: forming the wiring terminal on a rigid substrate; formingthe signal wire on the rigid substrate with the wiring terminal formedthereon; forming the flexible base substrate on the rigid substrate withthe wiring terminal and the signal wire formed thereon; and forming thethin film transistor and the signal wire on the flexible base substrate,wherein a plurality of wiring terminals are provided.
 25. Themanufacturing method according to claim 19, wherein after forming thethin film transistor on the flexible base substrate, the method furthercomprises: peeling off the rigid substrate.